DIPIETE TIME TABLE
Posts
8.10 STANDARD I/O INTERFACES (BUSES)
8.10 STANDARD I/O INTERFACES (BUSES) From the discussions so far, the reader must have understood that the input/output system for a com- puter are accommodated in many layers, like memory devices. We have already discussed about cache memory and a special high speed bus to communicate with it, designated as cache bus ( Figure 8.13 ). Main memory of the system is also interfaced with the processor with a dedicated memory bus so that delay in I/O operations, which is quite normal and happens frequently, does not retard the instruction that has to be carried out. The innermost layer of I/O devices is directly interfaced with the processor through its address, data and control bus (designated as I/O bus), and communicates in synchronous manner (synchronous parallel communication). Note that although with processor these devices communicate in synchronous fashion, with the external world they communicate in asynchronous manner. Example of I/O devices of this layer may be
Logic gate symbols
Logic gate symbols There are two series of symbols for logic gates: The traditional symbols have distinctive shapes making them easy to recognise so they are widely used in industry and education. The IEC (International Electrotechnical Commission) symbols are rectangles with a symbol inside to show the gate function. They are rarely used despite their official status, but you may need to know them for an examination. Inputs and outputs Gates have two or more inputs, except a NOT gate which has only one input. All gates have only one output. Usually the letters A, B, C and so on are used to label inputs, and Q is used to label the output. On this page the inputs are shown on the left and the output on the right. The inverting circle (o) Some gate symbols have a circle on their output which means that their function includes inverting of the output. It is equivalent to feeding the output through a NOT gate. For example the NAND ( N ot AND ) gate symbol shown